1. Field of the Invention
This invention relates to a laminated multi-chip module type semiconductor device, a lead-frame product used therefor and a method for manufacturing it.
2. Related Art
Traditionally, there is a known semiconductor package suited to layered multi-chip module packaging which includes a semiconductor chip, external terminals connected to the electrode pads thereof through lead wires (bonding wires) and a mold part (sealing resin) which seal them with resin, and in which the external terminals consist of at least terminals frames stacked in two layers and are exposed to the three faces of the bottom face, side face and upper face of the mold part (for example, see JP-A-2002-76175).
There is also a known resin-sealed type semiconductor device in which the external terminals provided above and below the semiconductor device are connected to a conductor pattern formed on the mold part by exposing the surface of the projection formed at a position apart from the tip of an inner lead to the surface of the mold part so as to freely stack an electronic component, resistor, semiconductor device with a different number of pins, etc. thereabove, thereby permitting its high density packaging (for example, see JP-A-2003-23133).
Since the external terminals of the semiconductor devices are exposed to the front and back surfaces, where the semiconductor devices are layered to make a vertical electrical connection, in the invention of JP-A-2002-76175, the lead frames are layered on one another, and in the invention of JP-A-2003-23133, the thickness of the terminal is changed between a wire-bonded area and an area exposed from the mold part or another conductor pattern substrate is bonded to the terminal. However, in the methods of layering the lead frames on one another, changing the thickness of the terminal and bonding the conductor pattern substrate on the external terminal, there occur a limit occurs in assuring the vertical electrical connection of the semiconductor devices layered and a problem of difficulty of realizing the fine pitch between the external terminals.